State-of-the-Art on Automatic Analog IC Sizing

In this chapter a state-of-the-art review on analog integrated circuit (IC) design automation tools applied to the specification translation problem is presented. Having the right topology for a given set of specifications is indispensable for a high performance design. An inadequate topology makes the design more difficult (or even impossible), and may require unnecessary resources, which is not acceptable in high performance designs. Once the topology is selected, the specifications for the overall block are translated to the specifications for the subblocks. The specifications are, in this way, passed through the hierarchy. At the lowest level, the translation reduces to circuit sizing, whereas at the higher levels it produce the sub-blocks performance parameters. In the last years, the scientific community proposed many techniques for the automation of the translation task; some apply only at circuit-level or only at system level, while others apply to both. In this study, several circuit-level sizing techniques are sketched and compared, and then, different model-based optimization approaches are outlined.